Combining Stack Location Allocation with Register Allocation

101 Pages·2005·0.42 MB·English

University of California
Los Angeles
Combining Stack Location Allocation
with
Register Allocation
A dissertation submitted in partial satisfaction
of the requirements for the degree
Doctor of Philosophy in Computer Science
by
Venkata Krishna Nandivada
2005
(cid:13)c Copyright by
Venkata Krishna Nandivada
2005
The dissertation of Venkata Krishna Nandivada is approved.
Majid Sarrafzadeh
Rupak Majumdar
Lei He
Bill Mangione-Smith
Jens Palsberg, Committee Chair
University of California, Los Angeles
2005
ii
To the almighty
iii
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 Register Allocation . . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 Stack Location Allocation . . . . . . . . . . . . . . . . . . 3
1.2 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Stack location allocation . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.2 Our Results . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.3 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.4 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 The SLA Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1 Model Extraction . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 Constraint Generation . . . . . . . . . . . . . . . . . . . . 21
2.2.3 Constraint Solving . . . . . . . . . . . . . . . . . . . . . . 23
2.2.4 Code Transformation . . . . . . . . . . . . . . . . . . . . . 24
2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.1 Benchmark Characteristics . . . . . . . . . . . . . . . . . . 25
2.3.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.3 Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . 27
iv
2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3 SARA: Combining Stack Allocation and Register Allocation . 30
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 ILP-based Register Allocation . . . . . . . . . . . . . . . . . . . . 35
3.2.1 Model extraction. . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.2 Constraint Generation. . . . . . . . . . . . . . . . . . . . . 36
3.2.3 Objective function. . . . . . . . . . . . . . . . . . . . . . . 38
3.2.4 Constraint Solving. . . . . . . . . . . . . . . . . . . . . . . 39
3.3 SARA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4 SARA Improvements . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4.1 Reducing the size of the ILP state space. . . . . . . . . . . 44
3.4.2 Improving the quality of the generated code. . . . . . . . . 46
3.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.6 Conclusion and Future work . . . . . . . . . . . . . . . . . . . . . 53
4 RALF: A register allocation framework . . . . . . . . . . . . . . 54
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2 Framework description . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.1 Input Interface . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2.2 Output Interface . . . . . . . . . . . . . . . . . . . . . . . 61
4.2.3 Correctness issues . . . . . . . . . . . . . . . . . . . . . . . 65
4.3 Versatility: Test by implementation . . . . . . . . . . . . . . . . . 67
v
4.3.1 Naive Register Allocator . . . . . . . . . . . . . . . . . . . 67
4.3.2 Linear Scan Register allocator . . . . . . . . . . . . . . . . 68
4.3.3 Iterative Register Coalescing . . . . . . . . . . . . . . . . . 71
4.3.4 Usage count based register allocator . . . . . . . . . . . . . 72
4.3.5 ILP based register allocator . . . . . . . . . . . . . . . . . 73
4.3.6 SARA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3.7 Register Allocation via Coloring of Chordal Graphs . . . . 74
4.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.5 Tools for the framework . . . . . . . . . . . . . . . . . . . . . . . 77
4.6 Observations and limitations . . . . . . . . . . . . . . . . . . . . . 78
4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . 80
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
vi
List of Figures
1.1 Layout of byte addressed SDRAM memory . . . . . . . . . . . . . 5
1.2 Issues with current way of stack allocation. . . . . . . . . . . . . . 7
2.1 Example C program and locations of variables with and with SLA
phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Code without and with SLA . . . . . . . . . . . . . . . . . . . . . 16
2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Phase ordering problem between register allocation and SLA . . . 32
3.2 Benchmark characteristics and compile time statistics . . . . . . . 49
3.3 Execution time numbers . . . . . . . . . . . . . . . . . . . . . . . 50
3.4 Normalized execution times . . . . . . . . . . . . . . . . . . . . . 51
3.5 A comparison of different register allocator schemes . . . . . . . . 52
4.1 Framework block diagram. . . . . . . . . . . . . . . . . . . . . . . 56
4.2 Sample input program, using two pseudos. . . . . . . . . . . . . . 60
4.3 Sample input interface data. . . . . . . . . . . . . . . . . . . . . . 62
4.4 Sample output interface data. . . . . . . . . . . . . . . . . . . . . 65
4.5 Pseudo code for naive register allocator. . . . . . . . . . . . . . . 68
4.6 Output of Naive register allocator for the code snippet in Fig. 4.2. 69
4.7 Assembly code generated from the register alloctor output in Fig.4.6 69
4.8 Iterated register coalescing. . . . . . . . . . . . . . . . . . . . . . 71
4.9 Chordal graph based register allocation. . . . . . . . . . . . . . . 74
vii
4.10 Experimental evaluation of RALF. . . . . . . . . . . . . . . . . . 76
4.11 Comparison of different register allocators . . . . . . . . . . . . . 76
viii
List of Tables
ix